1. Field of the Invention
This invention relates to plastic leadframe semiconductor packages such as those used in the manufacture of dynamic random access memories (DRAM) that are capable of a high data transfer rate in the range of 1 GigaHertz.
2. Background Art
Dynamic random access memory (DRAM) integrated circuits are widely used in leadframe packages such as thin small outline packages (TSOP) for memory module assembly. TSOP packages have many advantages in the fabrication of dual inline memory modules (DIMM). These packages are characterized by a low (i.e. thin) profile, low manufacturing cost, relatively small size, and are generally compatible with common surface mount technology (SMT) equipment and processes. Accordingly, in recent years, TSOP packages have been the package of choice for use in most DIMM memory module assemblies.
However, with the advent of high-speed and high-performance DRAM memory devices, the system clock speed of a synchronous DRAM (SDRAM) has increased from less than 100 MHz to over 300 MHz and higher. Newer generation devices such as the double data rate (DDR) SDRAM have clock speeds moving beyond 500 MHz. These high performance devices require that the package electrical inductance be minimized to better preserve the system signal integrity and timing parameters. Typically, a conventional TSOP package containing an IC chip is wire-bond interconnected to the leadframe tip bonding pads by means of thin (e.g. 25-30 μm diameter) gold wires. Hence, at high frequencies, such wire-bond interconnections exhibit a significant amount of inductance.
Consequently, many chip scale packages (CSP) use ribbon conductors instead of wires to reduce the package inductance. However, the CSP packages are more expensive to manufacture than TSOP packages and require more advanced surface mount technology equipment for board-level assembly and inspection. Accordingly, there exists a need for a high performance TSOP-type leadframe package that can be manufactured at low cost and can be easily assembled using standard SMT equipment and procedure so as to be suitable for use in most DRAM packages used today.
In a modern memory IC TSOP package, the IC input/output bonding pads are located along the centerline of the chip and the leadframe leads are extended to both the right-hand and the left-hand sides of the center bonding pads. This lead-over chip (LOC) arrangement is employed to minimize the distance between the leadframe terminals and the bond pads such that, after wire bonding, the wire loop distance and height will be minimized when compared to having the leadframe terminals located near the perimeter of the chip, which requires much longer wire length from the center of the chip. Even with such LOC optimization, there still is a substantially large wire length in a TSOP package when compared to chip scale packages that use shorter interconnections by means of either thin wires, conductive ribbons, or flip chip bumps. Because of this limitation, new generations of SDRAMs having high system speeds are typically used in only the more expensive CSP packages.
It is therefore desirable to have a configuration compatible, low-cost package that permits the use of late generation, high-speed DDR SDRAM memory integrated circuits in leadframe packages such as a TSOP for easy manufacturability in a conventional memory DIMM module assembly. In this same regard, it is also desirable to enhance the high-speed performance characteristics by replacing the conventional thin wire bonds used for electrical interconnection between the IC input/output bonding pads and the package leadframe terminal pads with other interconnection means that allow for better electrical signal integrity and timing parameters similar to those of chip scale packages.